m1010-01 datasheet rev 0.5 revised 30mar2005 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 m1010-01 vcso b ased c lock j itter a ttenuator integrated circuit systems, inc. preliminary information g eneral d escription the m1010-01 is a vcso (voltage controlled saw oscillator) bas ed clock jitter attenuator pll designed for clock jitter attenuation and frequency translation. the device is ideal for generating the transmit reference clock for oc-12 and oc-48 optical network systems supporting 622 - 2,488 mhz rates. it can serve to jitter attenuate a stratum reference clock or a recovered clock in loop timing mode. the m1010-01 module includes a proprietary saw (surface acoustic wave) delay line as part of the vcso. this results in a high frequency, high-q, low phase noise os cillator that assures low intrinsic output jitter. f eatures ideal for oc-12/48 data clock integrated saw delay line output frequencies from 150 to 175 mhz (specify vcso output frequency at time of order) low phase jitter of 0.5 ps rms, typical (12khz to 20mhz) lvpecl clock output pin-selectable feedback and reference divider ratios, no programming required scalable dividers provide fu rther adjustment of loop bandwidth as well as jitter tolerance reference clock inputs support differential lvds, lvpecl, as well as single -ended lvcmos, lvttl single 3.3v power supply small 9 x 9 mm smt (surface mount) package p in a ssignment (9 x 9 mm smt) figure 1: pin assignment s implified b lock d iagram figure 2: simplified block diagram example i/o clock frequency combinations using m1010-01-155.5200 frequency input (mfin) ratio input reference clock (mhz) output clock mhz 8 19.44 155.52 2 77.76 1 155.52 table 1: example i/o clock frequency combinations m1010 (top view) 18 17 16 15 14 13 12 11 10 28 29 30 31 32 33 34 35 36 1 2 3 4 5 6 7 8 9 fin_sel1 gnd nc dif_ref0 ndif_ref0 ref_sel dif_ref1 ndif_ref1 vcc vcc nc nfout fout gnd nc nc vcc gnd fin_sel0 sel0 sel1 sel2 nc vcc dnc dnc dnc nop_in op_out vc nvc nop_out op_in gnd gnd gnd 19 20 21 22 23 24 25 26 27 r div vcso mfin div m div divider lut mfin divider lut fin_sel1:0 ref_sel dif_ref0 ndif_ref0 dif_ref1 ndif_ref1 0 1 m1010 fout nfout sel2:0 3 2 loop filter m1010-01 vcso based clock jitter attenuator
m1010-01 datasheet rev 0.5 2 of 8 revised 30mar2005 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m1010-01 vcso b ased c lock j itter a ttenuator preliminary information d etailed b lock d iagram figure 3: detailed block diagram p in d escriptions number name i/o configuration description 1, 2, 3, 10, 14, 26 gnd ground power supply ground connections. 4 9 op_in nop_in input external loop filter connections. see figure 4, external loop filter, on pg. 4. 5 8 nop_out op_out output 6 7 nvc vc input 11, 18, 19, 33 vcc power power supply connection, connect to + 3.3 v. 12, 13, 17, 25, 32 nc no internal connection. 15 16 fout nfout output no internal terminator clock output pairs. differential lvpecl. 20 ndif_ref1 input internal pull-up resistor 1 note 1: for typical values of internal pull-down and pull-up resi stors, see ?inputs with pull-down? and ?inputs with pull-up? in table 8, dc characteristics, on pg. 6. reference clock input pair. differential lvpecl or lvds. 21 dif_ref1 internal pull-down resistor 1 22 ref_sel input internal pull-down resistor 1 referenc e clock input selection. lvcmos/lvttl: logic 1 selects dif_ref1, ndif_ref1. logic 0 selects dif_ref0, ndif_ref0 . 23 ndif_ref0 input internal pull-up resistor 1 reference clock input pair. differential lvpecl or lvds. 24 dif_ref0 internal pull-down resistor 1 27 28 fin_sel1 fin_sel0 input internal pull-down resistor 1 i nput clock frequency selection. lvcmos/lvttl. see table 3, mfin (frequency input) divider look-up table (lut) on pg. 3. 29 30 31 sel0 sel1 sel2 input internal pull-up resistor 1 m and r divider value selection. lvcmos/ lvttl. see table 4, sel2:0 look-up table (lut) on pg. 3. 34, 35, 36 dnc do not connect. table 2: pin descriptions phase locked loop (pll) m1010 saw delay line phase shifter vcso c post c post vc nvc r post nop_out op_out r post r loop r loop c loop c loop r in r in op_in nop_in phase detector loop filter amplifier external loop filter components fout nfout sel2:0 fin_sel1:0 r div mux 0 ref_sel dif_ref1 ndif_ref1 dif_ref0 ndif_ref0 1 2 divider lut 3 mfin divider lut mfin divider m div
m1010-01 datasheet rev 0.5 3 of 8 revised 30mar2005 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 m1010-01 vcso b ased c lock j itter a ttenuator preliminary information integrated circuit systems, inc. pll d ivider l ook -u p t ables mfin (frequency input) divider look-up table (lut) the fin_sel1:0 pins select the feedback divider value (?mfin?). sel2:0 look-up table (lut) the sel2:0 pins select the feedback and reference divider values m and r to enable adjustment of loop bandwidth and jitter tolerance. f unctional d escription the m1010-01 is a pll (phase locked loop) based clock generator that generates output clocks synchro- nized to one of two selectable input reference clocks. an internal high "q" saw filter provides low jitter signal performance and controls the output frequency of the vcso (voltage contro lled saw oscillator). a configurable frequency divider (labeled ?mfin divider?) provides the division options to accomodate various reference clock frequencies. in addition, configurable feedback and reference dividers (the ?m divider? and ?r divider?) provide divider value options to enable adjustment of loop bandwidth and jitter tolerance. for example, the m1010-01-155.5200 (see ?ordering information? on pg. 8 ) has a 155.52 mhz vcso frequency: the mfin feedback divider allows an input frequency to be the vcso output frequency divided by 1 , 2 , or 8 . therefore, for the base input frequency of 155.52 mhz, the actual input reference clock frequencies can be: 155.52 , 77.76 , and 19.44 mhz. (see table 3 on pg. 3.) the pll the pll uses a phase detector and configurable dividers to synchronize the output of the vcso with selected reference clock. the ?mfin divider? and ?m divider? divide the vcso frequency, feeding the result into the phase detector. the selected input reference clock is divided by the ?r divider?. the result is fed into the other input of the phase detector. the phase detector compares its two inputs. it then outputs pulses to the loop filter as needed to increase or decrease the vcso frequency and thereby match and lock the divider output?s frequency and phase to those of the input reference clock. due to the narrow tuning range of the vcso (+ 200ppm), appropriate selection of all of the following are required for the pll be able to lock: vcso center frequency, input frequency, and divider selections. relationship among frequencies and dividers the vcso center frequency must be specified at time of order. the relationship between the vcso (fvcso) frequency, the mfin divider, the m divider, the r divider, and the input reference frequency (fin) is: clock output the m1010-01 provides one differential lvpecl output pair fout . pecl and lvds product options are available; consult factory. fin_sel1:0 mfin value m1010-01-155.5200 sample ref. freq. (mhz) 1 note 1: example with m1010-01-155.5200. 0 0 8 19.44 0 1 2 77.76 10 1 155.52 1 1 x test mode. do not use. table 3: mfin (frequency input) divider look-up table (lut) sel2:0 m r description 0 0 0 236 236 various divider values to adjust bandwidth and jitter tolerance 001 79 79 010 14 14 0 1 1 239 239 100 1 1 101 2 2 110 4 4 111 8 8 table 4: sel2:0 look-up table (lut) fvcso fin mfin m r ---- =
m1010-01 datasheet rev 0.5 4 of 8 revised 30mar2005 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m1010-01 vcso b ased c lock j itter a ttenuator preliminary information external loop filter to provide stable pll operation, the m1010-01 requires the use of an external loop filter. this is implemented by connecting passive external components to the device as shown in figure 4 below. the m1010-01 utilizes a diff erential anal og signal path to minimize noise coupling from the system. because of this, the loop filter implementation requires two identical complementary rc filters as shown here. figure 4: external loop filter pll bandwidth is affected by the ?m? value and the ?mfin? value, as well as the vcso frequency. the various sel1:0 settings can be used to actively change pll loop bandwidth in a given application. see ?sel2:0 look-up table (lut)? on pg. 3. see table 5, example loop filter component values for m1010-01-155.5200, on pg. 4. pll simulator tool available a free pc software utility is available on the ics website (www.icst.com). the m2000 timing modules pll simulator is a downloadable application that simulates pll jitter and wander transfer characteristics. this enables the user to set appropriate external loop component values in a given application. c post c post v c nvc r post nop_out op_out r post r loop r loop c loop c loop op_in nop_in 6 7 5 49 8 example loop filter component values for m1010-01-155.5200 1 vcso parameters: k vco = 200khz/v, r in = 2050k ? , vcso bandwidth = 700khz. device configuration example external loop filter component value nominal performance using these values f ref (mhz) f vcso (mhz) mfin m, r value 2 r loop c loop r post c post pll loop bandwidth damping factor passband peak amplitude @ center (db) freq . 19.44 155.52 8 1 118.0 k ? 1.0 f 100 k ? 1000 pf 270 hz 6.5 0.05 10 hz 2 118.0 k ? 22.0 f 200 k ? 1000 pf 134 hz 6.8 0.04 4 hz 77.76 155.52 2 1 59.0 k ? 1.0 f 100 k ? 1000 pf 610 hz 6.5 0.05 20 hz 2 59.0 k ? 2.2 f 100 k ? 1000 pf 267 hz 6.8 0.04 10 hz 8 118.0 k ? 2.2 f 200 k ? 1000 pf 134 hz 6.8 0.04 10 hz 155.52 155.52 1 1 40.2 k ? 1.0 f 40.2 k ? 1000 pf 740 hz 6.3 0.05 20 hz 4 59.0 k ? 1.0 f 100 k ? 1000 pf 267 hz 6.8 0.04 10 hz 8 76.8 k ? 2.0 f 200 k ? 1000 pf 180 hz 6.3 0.05 8 hz table 5: example loop filter component values for m1010-01-155.5200 note 1: k vco , vcso bandwidth, m divider value, and external loop filter component values determine loop bandwidth, damping factor, and passband peaking. for pll simulator software, go to www.icst.com. note 2: for loop timing applications, the recommended val ue for the product of ?mfin? x ?m? is 8 or higher.
m1010-01 datasheet rev 0.5 5 of 8 revised 30mar2005 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 m1010-01 vcso b ased c lock j itter a ttenuator preliminary information integrated circuit systems, inc. a bsolute m aximum r atings 1 symbol parameter rating unit v i inputs - 0.5 to v cc + 0.5 v v o outputs - 0.5 to v cc + 0.5 v v cc power supply voltage 4.6 v t s storage temperature - 45 to + 100 o c table 6: absolute maximum ratings note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress sp ecifications only. functional operati on of product at these conditions or any conditions beyond those listed in recommended conditions of operation, dc characteristics, or ac characteristics is not implied. exposure to absolute maximum rating condi tions for extended periods may affect product reliability . r ecommended c onditions of o peration symbol parameter min typ max unit v cc positive supply voltage 3.135 3.3 3.465 v t a ambient operating temperature commercial 0 + 70 o c industrial -40 + 85 o c table 7: recommended conditions of operation
m1010-01 datasheet rev 0.5 6 of 8 revised 30mar2005 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m1010-01 vcso b ased c lock j itter a ttenuator preliminary information e lectrical s pecifications dc characteristics unless stated otherwise, v cc = 3.3 v + 5 %,t a = 0 o c to + 70 o c (commercial), f vcso = f out = 150-175 mhz, outputs terminated with 50 ? to v cc - 2v t a = -40 o c to + 85 o c (industrial) symbol parameter min typ max unit conditions power supply v cc positive supply voltage 3.135 3.3 3.465 v i cc power supply current 162 ma differential inputs i ih input high current dif_ref0, dif_ref1 150 a ndif_ref0, ndif_ref1 5 a i il input low current dif_ref0, dif_ref1 -5 a ndif_ref0, ndif_ref1 -150 a v p - p peak to peak input dif_ref0, ndif_ref0, dif_ref1, ndif_ref1 0.15 v v cmr common mode input 0.5 v cc - v lvcmos / lvttl inputs v ih input high voltage ref_sel, fin_sel1, fin_sel0, sel2, sel1, sel0 2 v cc + 0.3 v v il input low voltage - 0.3 0.8 v c in input capacitance 4 pf inputs with pull-down i ih input high current all inputs except ndif_ref1:0, sel2:0 150 a v cc = v in = 3.456v i il input low current - 5 a r pulldown internal pull-down resistor 51 k ? inputs with pull-up i ih input high current ndif_ref1, ndif_ref0, sel2, sel1, sel0 5 a v cc = 3.456v v in = 0 v i il input low current -1 50 a r pullup internal pull-up resistor 51 k ? all inputs c in input capacitance all inputs 4 pf differential outputs v oh output high voltage fout, nfout v cc - 1.4 v cc - 1.0 v v ol output low voltage v cc - 2.0 v cc - 1.7 v v p - p peak to peak output voltage 1 note 1: single-ended measurement. see figure 5, output rise and fall time on pg. 7. 0.4 0.85 v table 8: dc characteristics
m1010-01 datasheet rev 0.5 7 of 8 revised 30mar2005 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 m1010-01 vcso b ased c lock j itter a ttenuator preliminary information integrated circuit systems, inc. e lectrical s pecifications ( continued ) p arameter m easurement i nformation output rise and fall time figure 5: output rise and fall time output duty cycle figure 6: output duty cycle ac characteristics unless stated otherwise, v cc = 3.3 v + 5 %,t a = 0 o c to + 70 o c (commercial), f vcso = f out = 150-175 mhz, outputs terminated with 50 ? to v cc - 2v t a = -40 o c to + 85 o c (industrial) symbol parameter min typ max unit conditions f in input frequency dif_ref0, ndif_ref0, dif_ref1, ndif_ref1 18.75 175 mhz 50 mhz f out output frequency fout, nfout 150 175 mhz apr vcso pull-range commercial 120 200 ppm industrial 50 150 ppm pll loop constants 1 note 1: parameters needed for pll simulator software; see tabl e 5, example loop filter component values for m1010-01-155.5200 on pg. 4. k vco vco gain 200 khz/v r in internal loop resistor 2050 k ? bw vcso vcso bandwidth 700 khz phase noise and jitter n single side band phase noise @ 155.52 mhz 1 khz offset - 83 dbc/hz fin=19.44_mhz mfin=8, m=x, r=x 10 khz offset - 113 dbc/hz 100 khz offset - 136 dbc/hz j(t) jitter (rms) @ 155.52 mhz 12 khz to 20 mhz 0.5 ps 50 khz to 80 mhz 0.5 ps odc output duty cycle 2 note 2: see parameter measurement information on pg. 7. 45 50 55 % t r output rise time 2 for fout, nfout 325 450 500 ps 20 % to 80 % t f output fall time 2 for fout, nfout 325 450 500 ps 20 % to 80 % table 9: ac characteristics 20% 80% t r 20% t f 80% clock output v p - p nfout fout t pw t period (output pulse width) t period t pw odc =
m1010-01 datasheet rev 0.5 8 of 8 revised 30mar2005 integrated circuit systems, inc. communications modules www.icst.com tel (508) 852-5400 integrated circuit systems, inc. while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high reliability, or other extraordina ry environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments. m1010-01 vcso b ased c lock j itter a ttenuator preliminary information d evice p ackage - 9 x 9mm c eramic l eadless c hip c arrier mechanical dimensions: figure 7: device package - 9 x 9mm ceramic leadless chip carrier o rdering i nformation consult ics for the availabilit y of other vcso frequencies. figure 8: part numbering scheme vcso freq (mhz) temperature order part number 155.52 commercial m1010-01 - 155.5200 industrial m1010-01 i 155.5200 156.25 commercial m1010-01 - 156.2500 industrial m1010-01 i 156.2500 table 10: ordering information vcso frequency (mhz) ? - ? = 0 to + 70 o c (commercial) consult ics for available vcso frequencies i = - 40 to + 85 o c (industrial) temperature device number part number: m1010- 01 - xxx.xxxx
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